1. Field
Example embodiments relate to a method of forming a poly-silicon pattern, a diode having a poly-silicon pattern, a resistive memory device having a poly-silicon pattern, and a method of manufacturing the diode and the memory device. For example, a method of forming poly-silicon pattern using an excimer laser annealing process, a vertical diode formed of a poly-silicon pattern, a multi-layer cross point resistive memory device including a vertical diode formed of poly-silicon pattern, and a method of manufacturing the vertical diode and the memory device.
2. Description of the Related Art
Semiconductor memory devices may be classified as volatile memory devices and non-volatile memory devices. In a volatile memory device, recorded data may be erased if electric power is turned off. In a non-volatile memory device, recorded data may not be erased if electric power is turned off. Non-volatile memory devices may be widely used in computers, mobile communication terminals, and memory cards.
For example, data storage media may be used to store data for a long period of time, and may be used to move data to other places, for example, memory sticks. Thus, interest for non-volatile memory devices may be increasing.
The structure of a memory cell, which is a basic element in the non-volatile memory device, may vary with the field in which the non-volatile memory device is used.
For example, a memory cell may be included in a Not-And (NAND) type flash memory device, which is a higher capacitance non-volatile memory device that is widely used. In a NAND type flash memory device, a gate structure of a transistor may have a stacked structure that may include a floating gate in which electric charges, for example, data, may be stored, an inter-gate dielectric layer, and a control gate.
However, a flash memory device may have a lower degree of integration and a slower operating speed than a dynamic random access memory (DRAM), which is a volatile memory device. For example, because a flash memory device may use a conductive material, for example, a doped poly-silicon, as a material for forming the floating gate, a parasitic capacitance between gate structures may be increased if the memory device is more highly integrated.
Therefore, non-volatile memory devices that may improve on the weaknesses of the flash memory device are being actively researched. For example, a resistive random access memory (RRAM) that may have a resistive property that may vary according to an applied voltage may be suggested.
For example, a multi-layer cross point RRAM device may be used because it may be highly-integrated.
FIG. 1 is a perspective view of a conventional multi-layer cross point RRAM device. Referring to FIG. 1, a multi-layer cross point RRAM device may include a plurality of conductive lines M formed on a semiconductor substrate (not shown) with constant intervals therebetween. First stacked patterns P1 may be formed as lines and may be formed above the conductive lines M with constant intervals therebetween. The first stacked patterns P1 may be separated by a predetermined or desired distance from an upper surface of the conductive lines M. The first stacked patterns P1 may cross the conductive lines M at a right angle. Each of the patterns P1 may include a first resistor R1 and a first upper electrode TE1 that may be sequentially stacked.
Plug type first stacked structures S1 may be interposed between the conductive lines M and the first stacked patterns P1 on crossing points of the conductive lines M and the first stacked patterns P1. The first stacked structure S1 may be a stacked structure that may include a first tungsten plug W1, a first vertical diode D1, and a first lower electrode BE1. The first vertical diode D1 may be formed as a stacked structure including an n-type oxide layer n0, for example, TiO2, and a p-type oxide layer p0, for example, NiO. The first tungsten plug W1 may reduce a contact resistance between the first vertical diode D1 and the conductive lines M.
Second stacked patterns P2 may be formed as lines and may be arranged with constant intervals therebetween. The second stacked patterns P2 may be separated by a predetermined or desired distance from upper surfaces of the first stacked patterns P1. The second stacked patterns P2 may cross the first stacked patterns P1 at a right angle, and each of the second stacked patterns P2 may be a stacked structure including a second resistor R2 and a second upper electrode TE2.
Plug type second stacked structures S2 may be interposed between the first stacked patterns P1 and the second stacked patterns P2 on crossing points of the first and second stacked patterns P1 and P2. The second stacked structure S2 may be a stacked structure including a second tungsten plug W2, a second vertical diode D2, and a second lower electrode BE2. The second stack structure may be formed of the same material as the material of the first stacked structure S1. The second stacked structure S2 may have the same structure as the structure of the first stacked structure S1, and thus detailed description for the structure is omitted.
The first and second resistors R1 and R2 may be oxide layers, for example, NiO, that may function as data storing layers. The first and second vertical diodes D1 and D2 may have p-n junction structures including oxide layers and may function as rectifying devices that may rectify electric currents to flow in a forward direction.
A conventional multi-layer cross point RRAM device may be formed by stacking the diodes and resistors, and thus, the structure of the device may be simplified. Therefore, a multi-layer cross point RRAM device may be more highly-integrated.
However, a conventional multi-layer cross point RRAM device may use binary oxide layers, for example, TiO2 and NiO, as the vertical diodes. Thus, current density through the diode may not be sufficiently high and the diode may not have a sufficient rectifying property. Further, the oxide layers for forming the diodes may be formed under a higher temperature for obtaining superior layer quality, and thus, fabricating costs may increase due to the higher temperature process.
In addition, a vertical diode of a conventional multi-layer cross point RRAM device may be formed of single crystalline silicon because a diode formed of a single crystalline silicon may have higher current density, lower turn-on current, and lower leakage current than those of a diode formed of binary-based oxide layers. However, a diode cannot be formed of single crystalline silicon if the vertical diode is formed on a predeposition layer that is formed of a metal layer or a metal oxide layer.